Display panels

ABSTRACT

A display panel comprising a plurality of first and second signal lines, first and second detecting lines, a plurality of ESD protection circuits, and first and second common electrode lines. The first and second detecting lines are respectively coupled to the first signal lines and the second signal lines. Each ESD protection circuit is coupled to one of the first signal lines or one of the second signal lines. The first and second common electrode lines are respectively coupled to first and second voltage ports. Each first signal line is coupled to the first common electrode line through the corresponding ESD protection circuit. Each second signal line is coupled to the second common electrode line through the corresponding ESD protection circuit.

BACKGROUND

The invention relates to a liquid crystal display panel, and inparticular to a liquid crystal display panel with a test circuit.

FIG. 1 is a schematic diagram of a display array of a conventionalliquid crystal display (LCD) panel. As shown in FIG. 1, a display array1, formed by interlacing data lines D₁ to D_(m) and scan lines G₁ toG_(n), is configured on a glass substrate and Each interlaced data lineand scan line corresponds to one display unit, for example, interlaceddata line D₁ and scan line S₁ correspond to display unit 100. As withany other display unit, the equivalent circuit of the display unit 100comprises a switch transistor TFT, a storage capacitor Cs, and a liquidcrystal capacitor Clc. A gate of the switch transistor is coupled to thescan line G₁, and a drain thereof is coupled to the data line D₁, and asource thereof is coupled to a pixel electrode PE.

After the display array of the LCD panel having the above-describedconfiguration is formed, the glass substrate is tested to detect shortsand breaks in the data lines D₁ to D_(m) and the scan lines G₁ to G_(n).To complete these tests, a liquid crystal display (LCD) device fortesting signal line disclosed in U.S. Pat. No. 6,566,902 B2, as shown inFIG. 2, comprises a plurality of data lines DL, an odd-numbereddetecting line ODDL, and an even-numbered detecting line EDDL. Theodd-numbered detecting line ODDL is commonly connected to odd-numbereddata lines DL through data pads 2, and the even-numbered detecting lineEDDL is commonly connected to even-numbered data lines DL through datapads 2. The LCD device provides two common electrode lines CLa and CLbarranged on the LCD device to cross each data line DL. The LCD alsoprovides a plurality of electrostatic discharge (ESD) protectioncircuits 12, each connected between an odd-numbered data line and thecommon electrode line CLa and between an even-numbered data line and thecommon electrode line CLb. The LCD device further provides at least twoauxiliary ESD protection circuits 14 connected in series between the twoseparated common electrode lines CLa and CLb. In this LCD device, onecommon voltage source Vcom provides voltage to both common electrodelines CLa and CLb. In a test process, test signals are applied to theodd-numbered detecting line ODDL and the even-numbered detecting lineEDDL and then to the odd-numbered data lines and the even-numbered datalines, respectively, to thereby detect faults of the data lines DL, suchas a short between two adjacent data lines DL. Similarly, the same testconfiguration is employed in the scan lines.

In the related art, the data lines DL are connected to the commonelectrode lines CLa or CLb through ESD protection circuits 12, which arefurther connected to the same common voltage source Vcom throughauxiliary ESD protection circuits 14. Thus, the test signals on theodd-numbered detecting line ODDL and the even-numbered detecting lineEDDL interfere with each other in a test process, resulting in aninaccurate test of signal lines.

SUMMARY

Display panels are provided. An exemplary embodiment of a display panelcomprises a plurality of first signal lines, a plurality of secondsignal lines, a first detecting line, a second detecting line, aplurality of ESD protection circuits, a first common electrode line, anda second common electrode line. The second signal lines are alternatelyconfigured with the first signal lines. The first detecting line iscoupled to the first signal lines. The second detecting line is coupledto the second signal lines. Each ESD protection circuit is coupled toone of the first signal lines or one of the second signal lines. Thefirst common electrode line is coupled to a first voltage port. Thesecond common electrode line is coupled to a second voltage port. Eachfirst signal line is coupled to the first common electrode line throughthe corresponding ESD protection circuit. Each second signal line iscoupled to the second common electrode line through the correspondingESD protection circuit.

In some embodiments, a first impedance element is coupled between thefirst common electrode line and the first voltage port. A secondimpedance element is coupled between the second common electrode lineand the second voltage port. The first and second signal lines can bedata lines or scan lines.

DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription given hereinbelow and the accompanying drawings, given byway of illustration only and thus not intended to be limitative of theinvention.

FIG. 1 shows a conventional display array of a LCD panel.

FIG. 2 shows a LCD device for testing signal line disclosed in U.S. Pat.No. 6,566,902 B2.

FIGS. 3 and 4 depict an embodiment of a display panel.

FIG. 5 depicts an embodiment of a display panel.

DETAILED DESCRIPTION

Display panels are provided. In some embodiments, as shown in FIG. 3, adisplay panel 3 comprises a test circuit 30 and a display array 31configured on a glass substrate. Since the display array 31 in FIG. 3 isthe same as the display array 1 in FIG. 1, like reference numbers areused to designate like parts, and descriptions of the like parts areomitted here. In the embodiment of FIG. 3, the display array 31 isformed by interlacing data lines D₁ to D₂, and scan lines G₁ to G_(2y).The data lines D₁ to D_(2x) are divided into two groups, one comprisingthe odd-numbered data lines D₁ to D_(2x-1), and the other comprising theeven-numbered data lines D₂ to D_(2x). The test circuit 30 comprises anodd-numbered detecting line ODDL₁, an even-numbered detecting lineEDDL₁, a plurality of electrostatic discharge (ESD) protection circuits301, and a plurality of data pads 302. The odd-numbered data lines D₁ toD_(2x-1) are coupled to the odd-numbered detecting line ODDL₁ throughcorresponding data pads 302, and the even-numbered data lines D₂ toD_(2x) are coupled to the even-numbered detecting line EDDL₁ throughcorresponding data pads 302.

Each ESD protection circuit 301 is coupled between the odd-numbered datalines D₁ to D_(2x-1) and a common electrode line CL₁ or between theeven-numbered data lines D₂ to D_(2x) and a common electrode line CL₂.Note that the common electrode lines CL₁ and CL₂ are coupled todifferent common voltage ports. As shown in FIG. 3, the common electrodeline CL₁ is coupled to a common voltage port PV₁, while the commonelectrode line CL₂ is coupled to a common voltage port PV₂.

In the embodiment of FIG. 3, a high impedance element R₁ is coupledbetween the common electrode line CL₁ and the common voltage port PV₁,and a high impedance element R₂ is coupled between the common electrodeline CL₂ and the common voltage port PV₂.

On the glass substrate, the common voltage ports PV₁ and PV₂ aredifferent, that is, the common voltage ports PV₁ and PV₂ are not coupledon the glass substrate. Thus, in a test process, respective test signalsprovided to the odd-numbered data lines D₁ to D_(2x-1) and theeven-numbered data lines D₂ to D_(2x) do not interfere with each other.

Referring to FIG. 4, the display panel 3 further comprises a testcircuit 32 for testing the scan lines S₁ to S_(2y). For clarity, FIG. 4shows only the test circuit 32 and the display array 31, and the testcircuit 31 is omitted. Referring FIG. 4, the scan lines S₁ to S_(2y) aredivided into two groups, one comprising the odd-numbered scan lines S₁to S_(2y-1), and the other comprising the even-numbered scan lines S₂ toS_(2y). The test circuit 32 comprises an odd-numbered detecting lineODDL₂, an even-numbered detecting line EDDL₂, a plurality of ESDprotection circuits 303, and a plurality of scan pad 304. Theodd-numbered scan lines S₁ to S_(2y-1) are coupled to the odd-numbereddetecting line ODDL₂ through corresponding scan pads 304, and theeven-numbered scan lines S₂ to S_(2y) are coupled to the even-numbereddetecting line EDDL₂ through corresponding scan pads 304.

Each ESD protection circuit 303 is coupled between the odd-numbered scanlines S₁ to S_(2y-1) and a common electrode line CL₃ or between theeven-numbered scan lines S₂ to S_(y) and a common electrode line CL₄.Note that the common electrode lines CL₃ and CL₄ are coupled todifferent common voltage ports. As shown in FIG. 4, the common electrodeline CL₃ is coupled to a common voltage port PV₃, while the commonelectrode line CL₄ is coupled to a common voltage port PV₄.

In the embodiment of FIG. 4, a high impedance element R₃ is coupledbetween the common electrode line CL₃ and the common voltage port PV₃,and a high impedance element R₄ is coupled between the common electrodeline CL₄ and the common voltage port PV₄.

On the glass substrate, the common voltage ports PV₃ and PV₄ aredifferent, that is, the common voltage ports PV₃ and PV₄ are not coupledon the glass substrate. Thus, in a test process, respective test signalsprovided to the odd-numbered scan lines S₁ to S_(2y-1) and theeven-numbered scan lines S₂ to S_(2y) do not interfere with each other.

In some embodiments, as shown in FIG. 5, a display panel 5 comprises atest circuit 50 and a display array 51 configured on a glass substrate.Since the display array 51 in FIG. 5 is the same as the display array 1in FIG. 1, like reference numbers are used to designate like parts, andthe description of like parts are omitted here. In the embodiment ofFIG. 5, the display array 51 is formed by interlacing data lines D₁ toD_(3x) and scan lines G₁ to G₂₃. According to the three primary colors,red (R) green (G), and blue (B), the data lines D₁ to D_(3x) are dividedinto three groups, one comprising red data lines D₁ to D_(3x-2), anothercomprising green data lines D₂ to D_(3x-1), and another comprising bluedata lines D₃ to D_(3x). The test circuit 50 comprises a red detectingline RDDL, green detecting line GDDL, a blue detecting line BDDL, aplurality of ESD protection circuits 501, and a plurality of data pad502. The red data lines D₁ to D_(3x-2) are coupled to the red detectingline RDDL through corresponding data pads 502, the green data lines D₂to D_(3x-1) are coupled to the green detecting line GDDL throughcorresponding data pads 502, and the blue data lines D₃ to D_(3x) arecoupled to the blue detecting line BDDL through corresponding data pads502.

Each ESD protection circuit 501 is coupled between the red data lines D₁to D_(3x-2) and a common electrode line CL_(R), between the green datalines D₂ to D_(3x-1) and a common electrode line CL_(G), or between theblue data lines D₃ to D_(3x) and a common electrode line CL_(B). Notethat the common electrode lines CL_(R), CL_(G), and CL_(B) are coupledto different common voltage ports. As shown in FIG. 5, the commonelectrode line CL_(R) is coupled to a common voltage port PV_(R), thecommon electrode line CL_(G) is coupled to a common voltage port PV_(G),and the common electrode line CL_(B) is coupled to a common voltage portPV_(B),

In the embodiment of FIG. 5, a high impedance element R is coupledbetween each common electrode line and the corresponding common voltageport.

On the glass substrate, the common voltage ports PV_(R), PV_(G), andPV_(B) are different, that is, the common voltage ports PV_(R), PV_(G),and PV_(B) are not coupled on the glass substrate. Thus, in a testprocess, respective test signals provided to the red data lines D₁ toD_(3x-2), the green data lines D₂ to D_(3x-1), and the blue data linesD₃ to D_(3x) do not interfere with each other.

In the embodiment of FIG. 5, a test circuit (not shown) for scan linesS₁ to S_(2y) is the same as the test current 32 in FIG. 4. Thus, theconnection between the scan lines S₁ to S_(2y) and the correspondingtest circuit refers to the description of FIG. 4 and further descriptionis omitted here.

In the invention, according to system requirements, signal lines (datalines or scan lines) can be divided into a plurality of groups fortesting. Each group of signal lines is coupled to one common electrodeline. Since each common electrode line is coupled to a respective commonvoltage port on a glass substrate, test signals on the plurality ofcommon electrode lines do not interfere with each other. Moreover, theplurality of common voltage ports are not connected on the glasssubstrate, but in the printed circuit board (PCB) or flexible printedcircuit (FPC) outside the glass substrate.

While the invention has been described in terms of preferred embodiment,it is to be understood that the invention is not limited thereto. On thecontrary, it is intended to cover various modifications and similararrangements as would be apparent to those skilled in the art.Therefore, the scope of the appended claims should be accorded thebroadest interpretation so as to encompass all such modifications andsimilar arrangements.

1. A display panel comprising: a plurality of first signal lines; aplurality of second signal lines, alternately configured with the firstsignal lines; a first detecting line coupled to the first signal lines;a second detecting line coupled to the second signal lines; a pluralityof electrostatic discharge (ESD) protection circuits, each coupled toone of the first signal lines or one of the second signal lines; a firstcommon electrode line coupled to a first voltage port, wherein eachfirst signal line is coupled to the first common electrode line throughthe corresponding ESD protection circuit; and a second common electrodeline coupled to a second voltage port, wherein each second signal lineis coupled to the second common electrode line through the correspondingESD protection circuit.
 2. The display panel as claimed in claim 1,further comprising: a first impedance element coupled between the firstcommon electrode line and the first voltage port; and a second impedanceelement coupled between the second common electrode line and the secondvoltage port.
 3. The display panel as claimed in claim 1, wherein thefirst and second signal lines are data lines.
 4. The display panel asclaimed in claim 1, wherein the first and second signal lines are scanlines.
 5. A display panel comprising: alternately configured first,second, and third data lines; a first detecting line coupled to thefirst data line; a second detecting line coupled to the second dataline; a third detecting line coupled to the third data line; a pluralityof first electrostatic discharge (ESD) protection circuits, each coupledto the first, second, or third data lines; a first common electrode linecoupled to a first voltage port, wherein the first data line is coupledto the first common electrode line through the corresponding first ESDprotection circuit; a second common electrode line coupled to a secondvoltage port, wherein the second data line is coupled to the secondcommon electrode line through the corresponding first ESD protectioncircuit; and a third common electrode line coupled to a third voltageport, wherein the third data line is coupled to the third commonelectrode line through the corresponding first ESD protection circuit.6. The display panel as claimed in claim 5, further comprising: a firstimpedance element coupled between the first common electrode line andthe first voltage port; a second impedance element coupled between thesecond common electrode line and the second voltage port; and a thirdimpedance element coupled between the third common electrode line andthe third voltage port.
 7. The display panel as claimed in claim 5,further comprising: first and second scan lines; a fourth detecting linecoupled to the first scan line; a fifth detecting line coupled to thesecond scan line; a plurality of second ESD protection circuits, eachcoupled to the first or second scan lines; a fourth common electrodeline coupled to a fourth voltage port, wherein the first scan line iscoupled to the fourth common electrode line through the correspondingsecond ESD protection circuit; and a fifth common electrode line coupledto a fifth voltage port, wherein the second scan line is coupled to thefifth common electrode line through the corresponding second ESDprotection circuit.
 8. The display panel as claimed in claim 7, furthercomprising: a fourth impedance element coupled between the fourth commonelectrode line and the fourth voltage port; and a fifth impedanceelement coupled between the fifth common electrode line and the fifthvoltage port.